[concurrency-interest] concurrency puzzle
alarmnummer at gmail.com
Tue Sep 12 15:50:19 EDT 2006
> You were worried that the write to x would be in the cache, but that the
> print would be from the value in main memory.
That is the part I'm trying to understand.
However, that's not how
> cache coherence works. To simplify, what will happen is that the write
> to x will occur, and subsequent reads of x from the same processor will
> a) be taken from the cache (and return 20), or
> b) be taken from main memory, *after the values in the cache are written
> out to it* (and return 20, or some other value that was written out
> after the 20 -- this might include the 10 from the other thread).
Aha.. so you are saying that before 'invalidating' cache, all values
are written to main memory? I though they were not written to main
memory, but they were 'dropped'. So if they are already in main
memory, you are lucky, if they only were in cache, you have lost your
This is exactly what I don't understand.
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