[concurrency-interest] concurrency puzzle

Peter Veentjer alarmnummer at gmail.com
Tue Sep 12 16:04:06 EDT 2006

It seems my understanding of cache wasn't correct.

There is a read-cache and a write cache. It isn't just a chunk of
memory that gets flushed.. only the writes are flushed and the read
memory is invalidated.

I'm going to sleep about it...

On 9/12/06, Peter Veentjer <alarmnummer at gmail.com> wrote:
> > You were worried that the write to x would be in the cache, but that the
> > print would be from the value in main memory.
> That is the part I'm trying to understand.
>  However, that's not how
> > cache coherence works.  To simplify, what will happen is that the write
> > to x will occur, and subsequent reads of x from the same processor will
> > either
> >
> > a) be taken from the cache (and return 20), or
> >
> > b) be taken from main memory, *after the values in the cache are written
> > out to it* (and return 20, or some other value that was written out
> > after the 20 -- this might include the 10 from the other thread).
> Aha.. so you are saying that before 'invalidating' cache, all values
> are written to main memory? I though they were not written to main
> memory, but they were 'dropped'. So if they are already in main
> memory, you are lucky, if they only were in cache, you have lost your
> writes.
> This is exactly what I don't understand.

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