[concurrency-interest] Lock-free signaling
jseigh_cp00 at xemaps.com
Mon Feb 26 23:00:17 EST 2007
Kimo Crossman wrote:
>By the way Joe have you seen this?
>Software Transactional Memory should Not be Lock Free
>Intel Research Cambridge Technical Report: IRC-TR-06-052, 2006
>This paper was submitted to SCOOL 2005, but deemed to be too contraversial and so was made the subject of a panel instead.
I was only able to look at it briefly. I'm not sure what made it too
controversial. If I
understand it the readers are subject to obstruction. It's a standard
if the data has changed during the read. Also I'm not sure about the
versioned data having more significant effect on cache than non
Java's object model has so much indirection already, I don't think you'd
the extra overhead. Plus there's hardware strategies to deal with
Niagara's hardware threading model, and not having cache coherency more
strict than it has to be.
On the afore mentioned STM implementation, I should have a prototype
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