[concurrency-interest] visibility vs. cache coherency

David Holmes dcholmes at optusnet.com.au
Tue Mar 11 19:53:14 EDT 2008

Also you'll find more details/discussion on the Java Memory Model list:


The simple (and therefore potentially misleading) answer is that hardware
cache coherent systems don't introduce visibility problems related to the
operation of memory at the hardware level. Systems that require software
directed cache coherency (the alpha architecture is an example) can have
visibility problems if the compiler doesn't generate those coherency
instructions where they are needed.

But aside from the hardware level, visibility arises from the actions of the
VM and in particular the code generated by the JIT. For example, without
something forcing it to do otherwise (i.e. a happens-before ordering) the
JIT might cache a read of a field in a register and not reload it, thereby
missing concurrent updates to that field.

David Holmes

> -----Original Message-----
> From: concurrency-interest-bounces at cs.oswego.edu
> [mailto:concurrency-interest-bounces at cs.oswego.edu]On Behalf Of Larry
> Riedel
> Sent: Wednesday, 12 March 2008 2:03 AM
> To: Concurrency-interest at cs.oswego.edu
> Cc: R Samuel Klatchko
> Subject: Re: [concurrency-interest] visibility vs. cache coherency
> > there does not appear to be a way to search
> > the list archives.  I also did some googling
> I think adding this to the google search may help
>     concurrency-interest site:cs.oswego.edu
> Larry
> _______________________________________________
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> Concurrency-interest at altair.cs.oswego.edu
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