[concurrency-interest] visibility vs. cache coherency
Online at stolsvik.com
Wed Mar 12 07:14:28 EDT 2008
David Holmes wrote:
> If you don't care about latency or ordering issues (which tend to be
> exactly the things we do care about!) then visibility on a hardware
> cache coherent system is not an issue - a write to a variable will
> become visible within a bounded time.
What if, as you mention, the compiler caches the variable in some
register, and this happens to be within some main loop of the program?
Without explicit happens-before edges (syncs, locks or volatiles)
between the threads concerned, couldn't this variable just be cached
literally forever - in regards to the program flow?
PS: This might be interesting:
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