[concurrency-interest] Question about phasers and cache lines
radhakrishnan.mohan at gmail.com
Tue Nov 22 22:58:25 EST 2011
Very useful. I also asked and found the intel manual on false sharing.
Now I can view this type of code using Oracle Studio analyzer because
the intel tools mentioned in the manual are expensive.
2011/11/18 Holger Hoffstätte <holger.hoffstaette at googlemail.com>:
> On 18.11.2011 12:24, Mohan Radhakrishnan wrote:
>> 2. Where do I read about cache lines , false sharing and why locations
>> have to be 4-words apart so that they don't fall in the same cache
>> line (Herlihy and shavit) ? Can I write a Java program to induce false
>> sharing ?
> Can't help with the Phaser question but false sharing is absolutely real
> and can be observed easily. Run the attached snippet and you will see the
> pretty serious effect that memory contention between threads can have. You
> might need to adjust the number of threads for your machine.
> Credits go to Martin Thompson, see blog URL in comments.
> On my old-ish Core2Duo laptop with slow bus & memory:
> Times in ns for 5000000 writes with 2 threads:
> plain : 1171084314
> plain : 1208625956
> plain : 1230311953
> padded : 140929085
> padded : 140683802
> padded : 141457922
> That's a difference in throughput by a factor of ~8, though the impact of
> course depends on the details of the CPU, caches, memory controller,
> memory system etc.
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