[concurrency-interest] Intel's HLE and Java
dl at cs.oswego.edu
Thu Apr 26 06:59:33 EDT 2012
On 04/25/12 07:35, Andrew Haley wrote:
> I've been thinking about what to do with Intel's Hardware Lock Elision
> (HLE), if anything.
Some of us have been contemplating possibilities of leveraging
new hardware atomicity constructs for a while -- including,
over the years, Azul, Sun Rock, AMD's ASF proposal, and
now Intel HLE+TM support. Dave Dice's blog
(https://blogs.oracle.com/dave/) includes some posts
and pointers to some papers.
As suggested by Nathan, the most likely role for HLE
is as a platform-specific optimization for the "fast"
paths of usually-uncontended short critical sections.
I suspect that hotspot and other JVMs will find ways
to apply them for some "synchronized" block and methods.
And we'll look into adding a couple of intrinsics to
use them strictly internally inside j.u.c on platforms
The more interesting question is whether/how to
additionally expose the more general TM instructions,
that amount to supporting very small transactions;
i.e., those touching only, 1, 2, 3, or 4
variables/fields. One possibility that we looked into
for Rock was to expose "Weak-NCAS". For example,
a 2CAS on Objects might look something like:
boolean cas2(Field a, Object expectedA, Object newA,
Field b, Object expectedB, Object newB);
returning true on success, but as with weakCompareAndSet,
allowing spurious failure.
People could them build "small" transaction classes
out of these and related methods.
One argument against this is that emulating NCAS on
machines that do not support it is very expensive.
Still, it is the only option I know that maintains
some semblance of platform-neutrality.
Aside: On Rock, we found that having 2CAS was a clear win
when used to re-implement some j.u.c functionality
including a variant of ConcurrentSkipListMap,
but there are diminishing returns with 3CAS, 4CAS, etc.
More direct hardware support of multi-variable atomicity
does not automatically make it fast.
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