[concurrency-interest] tsc register

Mohan Radhakrishnan radhakrishnan.mohan at gmail.com
Tue Jan 10 06:39:12 EST 2012


One more question from the novice and for the novice.

I see these points in Dr. click's PPT. Can I know why ? I ask this
here because it seems to
involve multiple cores. Maybe the jvm forums are better suited for this.
Does this mean that we get wrong time values if threads run on
different cores ?

But cannot use, e.g. X86's "tsc" register
? Value not coherent across CPUs
? Not consistent, e.g. slow ticking in low-power mode
? Monotonic per CPU – but not per-thread


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