[concurrency-interest] padding in Exchanger

Doug Lea dl at cs.oswego.edu
Tue Jan 17 10:22:30 EST 2012

On 01/17/12 09:33, Vitaly Davidovich wrote:
> Curious - which i7 arch has 128 byte cache line? I know Netburst used to have
> 128 as a blocked pair of two 64 byte lines, but didn't see anything on the newer
> chips.

It seems that even the ones without cacheline fusing still do
adjacent-cacheline prefetching, with similar effect.


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