[concurrency-interest] padding in Exchanger

Vitaly Davidovich vitalyd at gmail.com
Tue Jan 17 10:29:08 EST 2012


But does prefetching actually cause sharing issues? Fusing them makes sense
why it would but prefetch seems like it'd be orthogonal to this.  Perhaps
I'm wrong though ...

Thanks

Sent from my phone
On Jan 17, 2012 10:23 AM, "Doug Lea" <dl at cs.oswego.edu> wrote:

> On 01/17/12 09:33, Vitaly Davidovich wrote:
>
>> Curious - which i7 arch has 128 byte cache line? I know Netburst used to
>> have
>> 128 as a blocked pair of two 64 byte lines, but didn't see anything on
>> the newer
>> chips.
>>
>
> It seems that even the ones without cacheline fusing still do
> adjacent-cacheline prefetching, with similar effect.
>
> -Doug
>
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