[concurrency-interest] padding in Exchanger

David Dice david.dice at gmail.com
Tue Jan 17 10:29:30 EST 2012

> For what it's worth, +1 on the annotation proposal.
> Curious - which i7 arch has 128 byte cache line? I know Netburst used to
> have 128 as a blocked pair of two 64 byte lines, but didn't see anything on
> the newer chips.
The line size and coherence unit is 64 bytes but adjacent sector prefetch
when enabled (sometimes a BIOS setting), can make the coherence unit
effectively 128 bytes, which is why I suggested extra padding to Doug.
 ASP is usually a good bet for single-threaded code, but occasionally it
can cause destructive interference, and it can be a challenge for MP code.

I think Intel officially recommends 128 bytes in their current optimization

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://cs.oswego.edu/pipermail/concurrency-interest/attachments/20120117/97eb595c/attachment.html>

More information about the Concurrency-interest mailing list