[concurrency-interest] If LoadLoad barrier is reduced to no-op, why lfence?
vitalyd at gmail.com
Fri Jul 27 13:25:27 EDT 2012
There are SSE write combining instructions that don't provide the same
order guarantee that write-back memory ones do (the typical mov
instruction) - this is where lfence would be needed.
Sent from my phone
On Jul 27, 2012 1:03 PM, "Lei Zhao" <leizhao833 at gmail.com> wrote:
> Hello Everyone,
> I am currently reading the JMM cookbook (
> http://gee.cs.oswego.edu/dl/jmm/cookbook.html) and have a (maybe hardware
> related) question about barrier instructions: if the LoadLoad barrier is
> going to be no-op on x86-TSO, why does lfence instruction exist at all?
> (similarly StoreStore and sfence). I am a little confused about whether
> x86-TSO intrinsically guarantees load-load ordering or not. Thank you.
> - Lei
> Concurrency-interest mailing list
> Concurrency-interest at cs.oswego.edu
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