[concurrency-interest] x86 NOOP memory barriers

Andrew Haley aph at redhat.com
Fri Aug 2 08:21:31 EDT 2013


On 08/02/2013 10:43 AM, Nitsan Wakart wrote:
> Hi,
> For clarity's sake I'd like an official explanation for the often quoted "all barriers except STORE/LOAD are a no-op on x86" statement from the JMM cookbook.
> Can someone (of authority, so I can later say: "But Mr. Authority here says...") please confirm/expand on/deny that while a volatile read or an AtomicLong.lazySet are a CPU noop (in the sense that they are a MOV like any other), they are also compiler instructions. One cannot simply replace a lazySet with a plain write to get the same effect. They might be cheap but they ain't free... 
> I would appreciate some more careful wording on this topic.


Intel® 64 Architecture Memory Ordering White Paper
This document has been merged into Volume 3A of Intel 64 and IA-32 Architectures Software Developer’s Manual.

http://download.intel.com/products/processor/manual/253668.pdf
Section 8.2




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