[concurrency-interest] CPU cache-coherency's effects on visibility

thurston at nomagicsoftware.com thurston at nomagicsoftware.com
Thu Feb 14 12:48:34 EST 2013


Ahh, the problem with superficial examples is well, they're 
superificial.
Let me rewrite the example a bit:
Thread 1:
run()
{
     log();
     Thread.sleep();
}

void log()
{
    log(this.shared)
}

and let me further stipulate that the JIT doesn't inline the log 
method.

I guess what I'm really asking is does CPU cache-coherency extend to 
registers?  Say, shared was a primitive (int,boolean), then 
theoretically shared could be cached in a register.  Would 
cache-coherency somehow reach down to another CPU's registers and 
'invalidate' the registers?


On 2013-02-14 09:38, Stanimir Simeonoff wrote:
> this.shared can be hoisted by JVM unless it's volatile. So Thread1
> always sees the initial value, e.g. null.
>
> The code can be x-formed into:
>  Thread 1:
> Foo shared = this.shared
>  while (true){
>      log(shared)
>      Thread.sleep(1000L)
>  }
>
> On Thu, Feb 14, 2013 at 6:48 PM, <thurston at nomagicsoftware.com> 
> wrote:
>
>> Given that all (?) modern CPUs provide cache-coherency, in the 
>> following (admittedly superficial example):
>>
>> Thread 1:
>> while (true)
>> {
>>     log(this.shared)
>>     Thread.sleep(1000L)
>> }
>>
>> Thread 2:
>>    this.shared = new Foo();
>>
>> with Thread 2's code only invoked once and sometime significantly 
>> after (in a wall-clock sense)
>> Thread 1; and there are no operations performed by either thread 
>> forming a happens-before relationship (in the JMM sense).
>>
>> Is Thread 1 *guaranteed* to eventually see the write by Thread 2?
>> And that that guarantee is provided not by the JMM, but by the 
>> cache-coherency of the CPUs?
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>
>
>
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