[concurrency-interest] CPU cache-coherency's effects on visibility

Stanimir Simeonoff stanimir at riflexo.com
Thu Feb 14 12:52:07 EST 2013


I guess what I'm really asking is does CPU cache-coherency extend to
> registers?

Cache coherency affects memory, registers are just that and very private.
They are unaffected.


> Say, shared was a primitive (int,boolean), then theoretically shared could
> be cached in a register.  Would cache-coherency somehow reach down to
> another CPU's registers and 'invalidate' the registers?

No.

Stanimir

>
>
>
> On 2013-02-14 09:38, Stanimir Simeonoff wrote:
>
>> this.shared can be hoisted by JVM unless it's volatile. So Thread1
>> always sees the initial value, e.g. null.
>>
>> The code can be x-formed into:
>>  Thread 1:
>> Foo shared = this.shared
>>  while (true){
>>      log(shared)
>>      Thread.sleep(1000L)
>>  }
>>
>> On Thu, Feb 14, 2013 at 6:48 PM, <thurston at nomagicsoftware.com> wrote:
>>
>>  Given that all (?) modern CPUs provide cache-coherency, in the following
>>> (admittedly superficial example):
>>>
>>> Thread 1:
>>> while (true)
>>> {
>>>     log(this.shared)
>>>     Thread.sleep(1000L)
>>> }
>>>
>>> Thread 2:
>>>    this.shared = new Foo();
>>>
>>> with Thread 2's code only invoked once and sometime significantly after
>>> (in a wall-clock sense)
>>> Thread 1; and there are no operations performed by either thread forming
>>> a happens-before relationship (in the JMM sense).
>>>
>>> Is Thread 1 *guaranteed* to eventually see the write by Thread 2?
>>> And that that guarantee is provided not by the JMM, but by the
>>> cache-coherency of the CPUs?
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>>
>>
>>
>> Links:
>> ------
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>>
>
>
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