[concurrency-interest] Semantics of compareAndSwapX

Vitaly Davidovich vitalyd at gmail.com
Wed Apr 2 08:40:32 EDT 2014


Seems like #1 is what most people would expect from CAS (and that would
match x86 semantics).

What do c++11 compilers emit for strong cas on AArch64?

Sent from my phone
On Apr 2, 2014 7:39 AM, "Andrew Haley" <aph at redhat.com> wrote:

> It seems to me that Doug and Hans disagree.
>
> So, I'm going to put this to a vote.
>
> Should CAS on Aarch64 be
>
>         <Access [A]>
>
>         // atomic_op (B)
> 1:      ldxr    x0, [B]         // Exclusive load
>         <op(B)>
>         stlxr   w1, x0, [B]     // Exclusive store with release
>         cbnz    w1, 1b
>         dmb     ish             // Full barrier
>
>         <Access [C]>
>
> or
>
>         <Access [A]>
>
>         // atomic_op (B)
> 1:      ldxar   x0, [B]         // Exclusive load with acquire
>         <op(B)>
>         stlxr   w1, x0, [B]     // Exclusive store with release
>         cbnz    w1, 1b
>
>         <Access [C]>
>
> or something else?
>
> Please reply with your choice.
>
> Thanks,
> Andrew.
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