[concurrency-interest] Semantics of compareAndSwapX

Andrew Haley aph at redhat.com
Wed Apr 2 10:11:51 EDT 2014


On 04/02/2014 01:40 PM, Vitaly Davidovich wrote:
> Seems like #1 is what most people would expect from CAS (and that would
> match x86 semantics).
> 
> What do c++11 compilers emit for strong cas on AArch64?

bool cas (std::atomic<int> *obj, int expected, int desired) {
  return obj->compare_exchange_strong(expected, desired, std::memory_order_seq_cst);
}


cas(std::atomic<int>*, int, int):
	sub	sp, sp, #16
	str	w1, [sp]
.L2:
	ldaxr	w3, [x0]
	cmp	w3, w1
	bne	.L3
	stlxr	w4, w2, [x0]
	cbnz	w4, .L2
.L3:
	cset	w0, eq
	add	sp, sp, 16
	ret

> 
> Sent from my phone
> On Apr 2, 2014 7:39 AM, "Andrew Haley" <aph at redhat.com> wrote:
> 
>> It seems to me that Doug and Hans disagree.
>>
>> So, I'm going to put this to a vote.
>>
>> Should CAS on Aarch64 be
>>
>>         <Access [A]>
>>
>>         // atomic_op (B)
>> 1:      ldxr    x0, [B]         // Exclusive load
>>         <op(B)>
>>         stlxr   w1, x0, [B]     // Exclusive store with release
>>         cbnz    w1, 1b
>>         dmb     ish             // Full barrier
>>
>>         <Access [C]>
>>
>> or
>>
>>         <Access [A]>
>>
>>         // atomic_op (B)
>> 1:      ldxar   x0, [B]         // Exclusive load with acquire
>>         <op(B)>
>>         stlxr   w1, x0, [B]     // Exclusive store with release
>>         cbnz    w1, 1b
>>
>>         <Access [C]>
>>
>> or something else?
>>
>> Please reply with your choice.
>>
>> Thanks,
>> Andrew.
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>>
> 



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