[concurrency-interest] Semantics of compareAndSwapX

Martin Buchholz martinrb at google.com
Wed Apr 2 12:34:33 EDT 2014


You want to watch Herb Sutter's talk
http://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-2-of-2http://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-2-of-2
around 0:53
but the entire codegen section of his talk from 0:26 touches on different
architectures.
Frustratingly the "ARM v8 CAS" box of Herb's table is empty.
We could ask Herb what's up with that!
But Herb does have an entry for ARM v7 CAS, and that would conservatively
work for ARM v8 as well.  Perhaps that's the intent.  (Of course, this is
for C++, not Java)


On Wed, Apr 2, 2014 at 8:18 AM, Vitaly Davidovich <vitalyd at gmail.com> wrote:

> Yes, that was my question :).  Indeed, it's a bit hard to figure out what
> exactly is required.
>
> Sent from my phone
> On Apr 2, 2014 11:09 AM, "Andrew Haley" <aph at redhat.com> wrote:
>
>> On 04/02/2014 03:53 PM, Vitaly Davidovich wrote:
>> > So no dmb here? Is that expected for sequentially consistent mode?
>>
>> I don't understand what you are asking.  Do we need an extra DMB for
>> sequential consistency?  AFAIK, no: this code is correct.  But there
>> is so much fog surrounding this that it's hard to say.
>>
>> > Sent from my phone
>> > On Apr 2, 2014 10:12 AM, "Andrew Haley" <aph at redhat.com> wrote:
>> >
>> >> On 04/02/2014 01:40 PM, Vitaly Davidovich wrote:
>> >>> Seems like #1 is what most people would expect from CAS (and that
>> would
>> >>> match x86 semantics).
>> >>>
>> >>> What do c++11 compilers emit for strong cas on AArch64?
>> >>
>> >> bool cas (std::atomic<int> *obj, int expected, int desired) {
>> >>   return obj->compare_exchange_strong(expected, desired,
>> >> std::memory_order_seq_cst);
>> >> }
>> >>
>> >>
>> >> cas(std::atomic<int>*, int, int):
>> >>         sub     sp, sp, #16
>> >>         str     w1, [sp]
>> >> .L2:
>> >>         ldaxr   w3, [x0]
>> >>         cmp     w3, w1
>> >>         bne     .L3
>> >>         stlxr   w4, w2, [x0]
>> >>         cbnz    w4, .L2
>> >> .L3:
>> >>         cset    w0, eq
>> >>         add     sp, sp, 16
>> >>         ret
>> >>
>> >>>
>> >>> Sent from my phone
>> >>> On Apr 2, 2014 7:39 AM, "Andrew Haley" <aph at redhat.com> wrote:
>> >>>
>> >>>> It seems to me that Doug and Hans disagree.
>> >>>>
>> >>>> So, I'm going to put this to a vote.
>> >>>>
>> >>>> Should CAS on Aarch64 be
>> >>>>
>> >>>>         <Access [A]>
>> >>>>
>> >>>>         // atomic_op (B)
>> >>>> 1:      ldxr    x0, [B]         // Exclusive load
>> >>>>         <op(B)>
>> >>>>         stlxr   w1, x0, [B]     // Exclusive store with release
>> >>>>         cbnz    w1, 1b
>> >>>>         dmb     ish             // Full barrier
>> >>>>
>> >>>>         <Access [C]>
>> >>>>
>> >>>> or
>> >>>>
>> >>>>         <Access [A]>
>> >>>>
>> >>>>         // atomic_op (B)
>> >>>> 1:      ldxar   x0, [B]         // Exclusive load with acquire
>> >>>>         <op(B)>
>> >>>>         stlxr   w1, x0, [B]     // Exclusive store with release
>> >>>>         cbnz    w1, 1b
>> >>>>
>> >>>>         <Access [C]>
>> >>>>
>> >>>> or something else?
>> >>>>
>> >>>> Please reply with your choice.
>> >>>>
>> >>>> Thanks,
>> >>>> Andrew.
>> >>>> _______________________________________________
>> >>>> Concurrency-interest mailing list
>> >>>> Concurrency-interest at cs.oswego.edu
>> >>>> http://cs.oswego.edu/mailman/listinfo/concurrency-interest
>> >>>>
>> >>>
>> >>
>> >>
>> >
>>
>>
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