[concurrency-interest] Semantics of compareAndSwapX
dl at cs.oswego.edu
Fri Feb 14 09:46:31 EST 2014
On 02/14/2014 08:12 AM, Andrew Haley wrote:
> On 02/14/2014 11:52 AM, David Holmes wrote:
>> Andrew Haley writes:
>>> What are the semantics of Unsafe.compareAndSwapX? The javadoc is
>>> rather thin.
>> They are the implementation for the associated AtomicX.compareAndSet methods
>> and so have to adhere to the specification of those methods. But in terms of
>> memory barriers the key factor is that the variables act as volatiles so the
>> semantics are of a volatile read combined with a volatile write.
> Yes, but is that all?
That's all wrt ordering effects, but CAS must also be atomic.
For ARMv8/Aarch64 (which I suspect you have in mind), the best mapping
is likely the one now used in linux.
// atomic_op (B)
1: ldxr x0, [B] // Exclusive load
stlxr w1, x0, [B] // Exclusive store with release
cbnz w1, 1b
dmb ish // Full barrier
Aside: The JMM update is likely to finally pin down
multiple modes of CAS/WeakCAS (full, acquire, release),
which are not all that common, but are specializable into
more efficient mappings on some processors.
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