[concurrency-interest] Semantics of compareAndSwapX
stephan.diestelhorst at gmail.com
Wed Feb 19 15:40:17 EST 2014
On 18 February 2014 12:56, Andrew Haley <aph at redhat.com> wrote:
> On 02/14/2014 01:51 PM, Stephan Diestelhorst wrote:
> > I am currently following up inside ARM about this, stay tuned.
> Any news?
Yes, so my original understanding was too simplistic. In the sequence
of memop_A; ldx.acq(B) ;... ; stx.rel(B); memopp_C we may indeed
observe a lack of ordering between memop_A and memop_C. So the
instruction sequence is not meant to be a full-fence replacement.
This is, however, consistent with our manuals, and the implementation
of the C++11 atomics, and the notion of sequential consistency of
So it really boils down to the semantics of Unsafe.CAS and that was
what you were asking earlier.
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