[concurrency-interest] Semantics of compareAndSwapX

David Holmes davidcholmes at aapt.net.au
Thu Feb 20 05:25:00 EST 2014


Andrew,

The volatile-read followed by volatile-write implicit in the CAS precludes
any accesses before the cas appearing after, or vice-versa. I would appeal
intuitively to "roach motel" semantics but Aleksey would jump on me. ;-)

David

> -----Original Message-----
> From: concurrency-interest-bounces at cs.oswego.edu
> [mailto:concurrency-interest-bounces at cs.oswego.edu]On Behalf Of Andrew
> Haley
> Sent: Thursday, 20 February 2014 7:49 PM
> To: Stephan Diestelhorst
> Cc: concurrency-interest at cs.oswego.edu; Stephan Diestelhorst
> Subject: Re: [concurrency-interest] Semantics of compareAndSwapX
>
>
> On 02/19/2014 08:40 PM, Stephan Diestelhorst wrote:
> > On 18 February 2014 12:56, Andrew Haley <aph at redhat.com> wrote:
> >> On 02/14/2014 01:51 PM, Stephan Diestelhorst wrote:
> >>> I am currently following up inside ARM about this, stay tuned.
> >>
> >> Any news?
> >
> > Yes, so my original understanding was too simplistic.  In the
> > sequence of memop_A; ldx.acq(B) ;... ; stx.rel(B); memopp_C we may
> > indeed observe a lack of ordering between memop_A and memop_C.  So
> > the instruction sequence is not meant to be a full-fence
> > replacement.  This is, however, consistent with our manuals, and the
> > implementation of the C++11 atomics, and the notion of sequential
> > consistency of atomics.
>
> Thank you.
>
> So, GCC's usage of ldaxr ... stlxr for CAS is OK, even though it
> doesn't completely enforce a full fence.  This is interesting.  I
> wonder how anyone (not on the language committee :-) is expected to
> know this.  Maybe they're not, and there is going to be some
> interesting confusion when people try to port software from Intel to
> ARM.
>
> > So it really boils down to the semantics of Unsafe.CAS and that was
> > what you were asking earlier.
>
> OK, thanks.  Thought so.
>
> So, Back to you, Doug: what are the semantics of Unsafe.CAS ?
>
> Andrew.
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