[concurrency-interest] Semantics of compareAndSwapX

Andrew Haley aph at redhat.com
Mon Feb 24 12:13:06 EST 2014


On 02/24/2014 02:47 PM, Oleksandr Otenko wrote:
> Hmmm...
> 
> Can someone clarify this issue? I don't know ARM instructions, yet it 
> seems the discussion contradicts itself.
> 
> This here observation summarizes that "GCC's usage of ....<instruction 
> sequence> is ok" despite it not being a full barrier, and that the 
> reordering of memop_A and memop_C before and after CAS respectively, is 
> allowed.
> 
> Yet further in the discussion Doug mentions it is meant to be a volatile 
> read+volatile write, which would preclude the reordering of memop_A and 
> memop_C.
> 
> So, is that reordering allowed or not?

Not by Java, no.  A ldx.acq ... stx.rel is not enough for Java's
compareAndSwap.  We are sure about that.

However, according to Stephan Diestelhorst it *is* enough for the
implementation of the C++11 atomics, and the notion of sequential
consistency of atomics.

I do not know what Stephan bases that claim on.

Andrew.


More information about the Concurrency-interest mailing list