[concurrency-interest] AtomicReference.updateAndGet() mandatory updating

Doug Lea dl at cs.oswego.edu
Fri Jun 2 07:48:22 EDT 2017


On 06/01/2017 09:02 AM, Andrew Haley wrote:

> LDARX is used for a seq.cst load.  And, no, I don't think that a fence
> on failure is needed to ensure that a failing CAS is strictly after
> the (volatile) store that failed it.
> 

For completeness (and to hopefully reduce confusion), mappings
using non-acq/rel versions of ld/st on POWER/ARM still require
a fence; easiest as unconditional trailing fence.

Also, here's an update of the proposed VarHandle paragraph.
It's more informative to phrase it in reverse order compared to
previous version:


 * <p>Access modes control atomicity and memory consistency
 * properties.  <em>Plain</em> <tt>get</tt> and <tt>set</tt> accesses
 * are guaranteed to be bitwise atomic only for references and
 * primitive values of at most 32 bits, and impose no observable
 * ordering constraints with respect to threads other than the
 * executing thread. <em>Opaque</em> operations are bitwise atomic and
 * coherently ordered with respect to accesses to the same variable.
 * In addition to obeying Opaque properties, <em>Release/Acquire</em>
 * operations are partially ordered: acquires and their subsequent
 * accesses are ordered after matching releases and their previous
 * accesses.  In addition to obeying Release/Acquire properties,
 * <em>Volatile</em> operations are totally ordered with respect to
 * each other.
 *


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