[concurrency-interest] AtomicReference.updateAndGet() mandatory updating
boehm at acm.org
Fri May 26 17:35:47 EDT 2017
Could we please get an example (i.e. litmus test) of how the "memory effect
of at least one volatile ... write" is visible, and where it's useful?
Since some people seem really attached to it, it shouldn't be that hard to
generate a litmus test.
So far we have a claim that it could affect progress guarantees, i.e.
whether prior writes eventually become visible without further
synchronization. I kind of, sort of, half-way believe that.
I haven't been able to make sense out of the subsequent illustration
attempts. I really don't think it makes sense to require such weird
behavior unless we can at least clearly define exactly what the weird
behavior buys us. We really need a concise, or at least precise and
As has been pointed out before, a volatile write W by T1 to x of the same
value that was there before is not easily observable. If I read that value
in another thread T2, I can't tell which write I'm seeing, and hence hence
a failure to see prior T1 writes is OK; I might have not seen the final
write to x. Thus I would need to communicate the fact that T1 completed W
without actually looking at x. That seems to involve another
synchronization of T1 with T2, which by itself would ensure the visibility
of prior writes to T2.
Thus, aside from possible really obscure progress/liveness issues, I really
don't see the difference. I think this requirement, if it is indeed not
vacuous and completely ignorable, would lengthen the ARMv8 code sequence
for a CAS by at least 2 instructions, and introduce a very obscure
divergence from C and C++.
I'm worried that we're adding something to make RMW operations behave more
like fences. They don't, they can't, and they shouldn't.
On Fri, May 26, 2017 at 1:08 PM, Nathan and Ila Reynolds <
nathanila at gmail.com> wrote:
> > "The memory effects of a write occur regardless of outcome."
> > "This method has memory effects of at least one volatile read and write."
> I am not sure what memory effects means. If this is defined somewhere in
> the specs, then ignore this since I haven't read JDK 9 specs.
> Does memory effects mean the cache line will be switched into the modified
> state even if an actual write doesn't occur? Or does memory effects have
> to do with ordering of memory operations with respect to the method's
> On 5/26/2017 1:59 PM, Doug Lea wrote:
>> On 05/26/2017 12:22 PM, Gil Tene wrote:
>> Actually this is another case where the Java 9 spec needs to be adjusted…
>> The pre-jdk9 method for weak CAS is now available in four
>> flavors: weakCompareAndSetPlain, weakCompareAndSet,
>> weakCompareAndSetAcquire, weakCompareAndSetRelease.
>> They have different read/write access modes. The specs reflect this.
>> The one keeping the name weakCompareAndSet is stronger, the others
>> weaker than before (this is the only naming scheme that works).
>> About those specs... see JBS JDK-8181104
>> The plan is for all CAS VarHandle methods to include the sentence
>> "The memory effects of a write occur regardless of outcome."
>> And for j.u.c.atomic methods getAndUpdate, updateAndGet,
>> getAndAccumulate, accumulateAndGet to include the sentence:
>> "This method has memory effects of at least one volatile read and
>> Which should clear up confusion.
>> Concurrency-interest mailing list
>> Concurrency-interest at cs.oswego.edu
> Concurrency-interest mailing list
> Concurrency-interest at cs.oswego.edu
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the Concurrency-interest