[concurrency-interest] AtomicReference.updateAndGet() mandatory updating
dl at cs.oswego.edu
Wed May 31 07:03:35 EDT 2017
On 05/30/2017 02:23 PM, Hans Boehm wrote:
> The memory model does not define "the memory consistency effects of
> a write". It only defines the effect of a volatile write to a
> specific field; the "memory consistency effects" depend entirely on
> the location being written.
OK. To be pedantic, this should read:
"The memory consistency effects of a write to the variable occur
regardless of outcome."
> The problem here is that there normally is no write to associate the
> "memory consistency effect" with.
But as an implementation-level concern, issuing full dmb
fence on ARM has memory consistency effects at least at strong.
> I'm not convinced this decision matters significantly in terms of
> programmability. Alex convinced me that it is, unfortunately,
> observable, because there are examples in which you can deduce that
> code is after a failed CAS. There may be code that relies on it, but
> I've never personally seen such code in production.
I agree in all senses. I think we have to do this, even though
it is unlikely to matter in practice. Given that the fence
only occurs on the fail path, the only possible negative
performance impact I can imagine is code bulk (adding two
instructions) and in turn possibly inlinability.
> C++ clearly specifies "CAS classic". There is no way to specify
> release semantics for a failed CAS, since there is no write.
The current C++ spec, sec 29.2 includes versions that do so,
bool atomic_compare_exchange_strong_explicit(volatile atomic-type *, T*,
T, memory_order, memory_order);
(BTW, there's a typo (a stray paren) in this decl on page 1130
of the draft available at http://www.open-std.org/jtc1/sc22/wg21/)
See also the easier-to-read version at
The second memory_order parameter is:
"Synchronization mode for the operation in case expected does not match
the contained value."
Both memory_order parameters default to seq_cst.
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