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I guess what I'm really asking is does CPU cache-coherency extend to registers?  </blockquote><div>Cache coherency affects memory, registers are just that and very private. They are unaffected.<br> </div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
Say, shared was a primitive (int,boolean), then theoretically shared could be cached in a register.  Would cache-coherency somehow reach down to another CPU's registers and 'invalidate' the registers?</blockquote>
<div>No.<br><br>Stanimir <br></div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><div class="h5"><br>
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On 2013-02-14 09:38, Stanimir Simeonoff wrote:<br>
</div></div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><div class="h5">
this.shared can be hoisted by JVM unless it's volatile. So Thread1<br>
always sees the initial value, e.g. null.<br>
<br>
The code can be x-formed into:<br>
 Thread 1:<br>
Foo shared = this.shared<br>
 while (true){<br>
     log(shared)<br>
     Thread.sleep(1000L)<br>
 }<br>
<br>
On Thu, Feb 14, 2013 at 6:48 PM, <<a href="mailto:thurston@nomagicsoftware.com" target="_blank">thurston@nomagicsoftware.com</a>> wrote:<br>
<br>
</div></div><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><div class="h5">
Given that all (?) modern CPUs provide cache-coherency, in the following (admittedly superficial example):<br>
<br>
Thread 1:<br>
while (true)<br>
{<br>
    log(this.shared)<br>
    Thread.sleep(1000L)<br>
}<br>
<br>
Thread 2:<br>
   this.shared = new Foo();<br>
<br>
with Thread 2's code only invoked once and sometime significantly after (in a wall-clock sense)<br>
Thread 1; and there are no operations performed by either thread forming a happens-before relationship (in the JMM sense).<br>
<br>
Is Thread 1 *guaranteed* to eventually see the write by Thread 2?<br>
And that that guarantee is provided not by the JMM, but by the cache-coherency of the CPUs?<br>
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