[concurrency-interest] Enforcing total sync order on modern hardware
aph at redhat.com
Mon Mar 16 14:44:37 EDT 2015
On 03/16/2015 05:00 PM, Marko Topolnik wrote:
> Given that, since Nehalem, cores communicate point-to-point over QPI
> and don't lock the global front-side bus, the CPU doesn't naturally
> offer a total ordering of all lock operations.
Intel do actually guarantee
Locked instructions have a total order.
so this is a hardware problem, not a software one. How exactly the
hardware people do this on a large network of processors is some of
the most Secret Sauce, but I can imagine some kind of combining
network in hardware.
 Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3 (3A, 3B & 3C): System Programming Guide 8.2.2, Memory
Ordering in P6 and More Recent Processor Families
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