[concurrency-interest] Enforcing total sync order on modern hardware

Marko Topolnik marko at hazelcast.com
Mon Mar 16 15:05:59 EDT 2015


Andrew,

thank you for the reference, this answers the dilemma in full. I didn't
know this guarantee existed on x86.

---
Marko

On Mon, Mar 16, 2015 at 7:44 PM, Andrew Haley <aph at redhat.com> wrote:

> On 03/16/2015 05:00 PM, Marko Topolnik wrote:
>
> > Given that, since Nehalem, cores communicate point-to-point over QPI
> > and don't lock the global front-side bus, the CPU doesn't naturally
> > offer a total ordering of all lock operations.
>
> Intel do actually guarantee
>
>     Locked instructions have a total order.
>
> so this is a hardware problem, not a software one.  How exactly the
> hardware people do this on a large network of processors is some of
> the most Secret Sauce, but I can imagine some kind of combining
> network in hardware.
>
> Andrew.
>
> [1]  Intel® 64 and IA-32 Architectures Software Developer’s Manual
> Volume 3 (3A, 3B & 3C): System Programming Guide 8.2.2, Memory
> Ordering in P6 and More Recent Processor Families
>
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