[concurrency-interest] Enforcing total sync order on modern hardware

Alexander Terekhov TEREKHOV at de.ibm.com
Tue Mar 24 23:01:36 EDT 2015


????

T1: X = 1;
T2: if (X) Y = 1;
T3: A = Y; B = X;

is about atomicity of absolutely independent write T1: X = 1; just like in
IRIW.

To make it dependent just add another thread:

T0: Z = 1;
T1: if (Z) X = 1;
T2: if (X) Y = 1;
T3: A = Y; B = X;

Marko Topolnik <marko at hazelcast.com>@cs.oswego.edu on 24.03.2015 21:27:42

Sent by:	concurrency-interest-bounces at cs.oswego.edu


To:	Alexander Terekhov/Germany/IBM at IBMDE
cc:	concurrency-interest <Concurrency-interest at cs.oswego.edu>
Subject:	Re: [concurrency-interest] Enforcing total sync order on modern
       hardware


On Tue, Mar 24, 2015 at 9:12 PM, Alexander Terekhov <TEREKHOV at de.ibm.com>
wrote:
      "Put another way, a system may pass this test and still fail IRIW"

      I don't think so, do you have a real world example?

All it takes is an architecture which doesn't enforce a global TSO for
independent writes, but does for dependent writes. Which, if any, chip has
those semantics I don't know, but its (non)existence certainly doesn't
(dis)prove anything. The tests will not suddenly become inequivalent the
day an architecture appears which differentiates between them.

---
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