[concurrency-interest] Enforcing total sync order on modern hardware

Alexander Terekhov TEREKHOV at de.ibm.com
Wed Mar 25 05:37:26 EDT 2015


try google... quick search yielded

https://books.google.de/books?isbn=1608459578

Michael L. Scott - 2013 - ‎Computers
Here the problem is not bypassing, but a lack of write atomicity—one thread
sees the value written by a store and another thread subsequently sees the
value ...


Marko Topolnik <marko at hazelcast.com>@cs.oswego.edu on 25.03.2015 08:07:05

Sent by:	concurrency-interest-bounces at cs.oswego.edu


To:	Alexander Terekhov/Germany/IBM at IBMDE
cc:	concurrency-interest <Concurrency-interest at cs.oswego.edu>
Subject:	Re: [concurrency-interest] Enforcing total sync order on modern
       hardware


On Wed, Mar 25, 2015 at 4:01 AM, Alexander Terekhov <TEREKHOV at de.ibm.com>
wrote:
      T1: X = 1;
      T2: if (X) Y = 1;
      T3: A = Y; B = X;

      is about atomicity of absolutely independent write T1: X = 1; just
      like in
      IRIW.

IRIW requires all writes to be independent, not just one, and I have
provided a clear argument why that is important (testing for TSO of
independent writes). So I can't really make sense of your current argument.

BTW "write atomicity" just means that all the constituent bits are observed
to be written at once. Obviously, you don't have that meaning in mind, but
it is not crystal-clear what exactly you _do_ mean by it.

---
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